Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-09-25
2007-09-25
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C716S030000
Reexamination Certificate
active
11201688
ABSTRACT:
A method and apparatus for the utilization of on-chip, programmable resources to implement a signal distortion characterization circuit. Programmable logic resources, such as programmable delay lines and phase shifting circuits, are utilized to obtain estimates of, for example, capacitive coupling of signal energy between various signal and clock routes within a programmable logic device (PLD). Progressively delayed/advanced samples are taken of a test signal transmitted through a victim net to form baseline test data. Samples of the test signal are then repeated in the presence of test signals transmitted through aggressor net(s) and compared to the baseline results to measure crosstalk distortion caused by capacitively coupled energy from the aggressor nets onto the victim net.
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Britt Cynthia
Maunu LeRoy D.
Xilinx , Inc.
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