Semiconductor fabrication process, lateral PNP transistor,...

Details Semiconductor fabrication process, lateral PNP transistor,... Semiconductor fabrication process, lateral PNP transistor,...

2007-05-15

2007-05-15

Smith, Zandra V. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S316000, C438S327000, C438S335000, C438S368000

Reexamination Certificate

active

10918057

ABSTRACT:
A method in the fabrication of an integrated bipolar circuit comprises the steps of: providing a p-type substrate; forming in the substrate a buried n+-type region and an n-type region above the buried n+-type region; forming field isolation areas around the n-type region; forming a PMOS gate region on the n-type region; forming a diffused n+-type contact from the upper surface of the substrate to the buried n+-type region; the contact being separated from the n-type region; forming a p-type polysilicon source on the n-type region; forming a p-type source in the n-type region; forming a p-type drain in the n-type region; and connecting the PMOS transistor structure to operate as a PNP transistor, wherein the source is connected to the gate and constitutes an emitter of the PNP transistor; the drain constitutes a collector of the PNP transistor; and the n-type region constitutes a base of the PNP transistor.

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M.C. Wilson, et al.; “Process HJ: A 30 GHz NPN and 20 GHz PNP Complementary Bipolar Process for High Linearity RF Circuits”; Proc.. IEEE BCTM Conf.; p. 164.

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