Reduced gate delay multiplexed interface and output buffer...

Details Reduced gate delay multiplexed interface and output buffer... Reduced gate delay multiplexed interface and output buffer...

2007-01-09

2007-01-09

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S310000, C365S200000, C365S208000, C365S189050, C365S230030

Reexamination Certificate

active

10345735

ABSTRACT:
A reduced gate delay multiplexed interface and output buffer circuit for random access memory arrays, such as synchronous dynamic random access memory (“SDRAM”) devices, or other integrated circuit devices incorporating embedded memory arrays which reduces data access time and clock latency. In accordance with the present invention, data is multiplexed (or selected) and driven out at the memory bank level rather than at the output pad area (or the embedded RAM macro edge) as in prior art techniques.

REFERENCES:
patent: 5016226 (1991-05-01), Hiwada et al.
patent: 5239507 (1993-08-01), Ohba
patent: 5404564 (1995-04-01), Hiwada et al.
patent: 5506808 (1996-04-01), Yamada et al.
patent: 5805522 (1998-09-01), Sukegawa et al.
patent: 5926434 (1999-07-01), Mori
patent: 6215721 (2001-04-01), Kim
patent: 09-073778 (1997-03-01), None
patent: 2001-093276 (2001-04-01), None

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