Method for manufacturing flash memory cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S258000, C438S593000, C438S261000, C438S775000, C438S791000, C438S508000, C438S508000, C257S314000, C257S315000, C257S316000

Reexamination Certificate

active

10880202

ABSTRACT:
Disclosed is a method for manufacturing a flash memory cell. A structure in which a floating gate, an ONO dielectric film and a control gate are stacked is formed by means of a gate mask process and an etch process. After a rapid thermal nitrification process is performed, a re-oxidization process is performed. Therefore, Si-dangling bonding broken during the gate etch process becomes a Si—N bonding structure by means of a rapid thermal nitrification process. As such, as abnormal oxidization occurring at the side of an ONO dielectric film during a re-oxidization process is prohibited, a smiling phenomenon of the ONO dielectric film is prevented.

REFERENCES:
patent: 5907183 (1999-05-01), Takeuchi
patent: 6228717 (2001-05-01), Hazama et al.
patent: 6610614 (2003-08-01), Niimi et al.
patent: 6627494 (2003-09-01), Joo et al.
patent: 2003/0119260 (2003-06-01), Kim et al.
patent: 2004/0171241 (2004-09-01), Kitamura et al.
Preliminary Notice of Rejection of the IPO for Application No. 093119261.

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