Method of automatically creating a semiconductor processing...

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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Reexamination Certificate

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10908537

ABSTRACT:
Described is a method for automatically generating a wafer prober file whereby testing parameters and die identities can be established for testing a complete semiconductor wafer and whereby acceptable or rejected dies can be identified and correlated later with where the good or bad dies are physically located on a wafer-under-test.

REFERENCES:
patent: 5851848 (1998-12-01), Balamurugan
patent: 6362013 (2002-03-01), Yoshimura
patent: 6380000 (2002-04-01), Subramanian
patent: 6639417 (2003-10-01), Takao
patent: 6774620 (2004-08-01), Nanbu
patent: 7039556 (2006-05-01), Whitefield et al.
patent: 2005/0288896 (2005-12-01), Whitefield et al.
patent: 2006/0036394 (2006-02-01), Chen et al.
patent: 2006/0128039 (2006-06-01), Lin et al.

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