Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2007-09-11
2007-09-11
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S503000, C713S601000
Reexamination Certificate
active
10335418
ABSTRACT:
A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch components may be selected by a multiplexor according to the phases of the destination clock. In another embodiment, a time delay may be passed into the destination clock domain and may be calculated by a number of destination clock cycle time periods. In certain circumstances, the time delay may be adjusted to compensate for longer delays in the clock crossing process.
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Bodas Amit
Bogin Zohar B.
Freker David E.
Kareenahalli Suryaprasad R.
Ramaswamy Sridhar
Caven & Aghevil LLC
Perveen Rehana
Rahman Fahmida
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