Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-09-18
2007-09-18
Lamarre, Guy (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S712000, C714S719000, C714S763000, C365S201000
Reexamination Certificate
active
11116197
ABSTRACT:
A test arrangement with a test memory chip and a control device is provided. Error correction data are stored in the test memory chip with the aid of the control device. In the case of an error event, it is ascertained whether the error occurred on the error correction chip. If so, the memory controller compares the data stored in the error correction chip with the data of the auxiliary memory. The address of the error correction chip can be deduced from the address of the auxiliary memory, thereby enabling unambiguous addressing of a defective memory cell of the error correction chip.
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Abraham Esaw T.
Eschweiler & Associates LLC
Infineon - Technologies AG
Lamarre Guy
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