Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2007-01-09
2007-01-09
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Reexamination Certificate
active
10639716
ABSTRACT:
A semiconductor storage device includes a circuit receiving a command signal for generating a read control signal (RPB) based on the transition of a clock signal CLK and a circuit receiving the command signal for generating a write control signal (WPB) based on the transition of the clock signal CLK. The read cycle in which decoding of an address, selection of a word line and activation of a sense amplifier are executed based on the read control signal to read cell data, and the write cycle in which decoding of an address, selection of a word line and activation of a write amplifier are executed based on the write control signal and bit line pre-charging is also carried out, are carried out alternately. The sense period of the read cycle is overlapped with the decoding period of the write cycle.
REFERENCES:
patent: 6029250 (2000-02-01), Keeth
patent: 6247073 (2001-06-01), Takeda
patent: 6330682 (2001-12-01), Kanazashi et al.
“QDR II SRAM: A Design Guide”, © Jun. 12, 2002, Cypress Semiconductor Corporation, p. 1-6.
“18Mb QDR II SRAM 2-Word Burst”, © 2003 Micron Technology, Inc., p. 1-27.
Kato Yosiyuki
Matsui Yuuji
Sonoda Masatoshi
Takahashi Hiroyuki
Muirhead & Saturnelli LLC
NEC Electronics Corporation
Peugh Brian R.
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