Semiconductor device having isolation region and method of...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S289000, C438S298000, C438S508000

Reexamination Certificate

active

10793923

ABSTRACT:
A trench isolation region is formed in a surface region of a semiconductor substrate to form a MOS type element region. A mask layer having an opening portion is formed on the semiconductor layer, the opening portion continuously ranging on the entire surface of the MOS type element region and on part of the trench isolation region provided around the MOS type element region. A first impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated in the semiconductor layer under the bottom surface of the shallow trench isolation region. A second impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated on the midway of the depth direction of the trench isolation region. Then, the first and second impurity ions are activated.

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patent: 6111295 (2000-08-01), Arai
patent: 6165825 (2000-12-01), Odake
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patent: 7064399 (2006-06-01), Babcock et al.
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patent: 9-139382 (1997-05-01), None
patent: 9-322348 (1997-12-01), None
patent: 2002-9173 (2002-01-01), None
U.S. Appl. No. 11/392,562, filed Mar. 30, 2006, Ueno.

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