Single transistor RAM cell and method of manufacture

Details Single transistor RAM cell and method of manufacture Single transistor RAM cell and method of manufacture

2006-08-08

2006-08-08

Lindsay, Jr., Walter L (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000

Reexamination Certificate

active

07087483

ABSTRACT:
A single transistor planar RAM memory cell with improved charge retention and a method for forming the same, the method including providing forming a pass transistor structure adjacent a storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second doped regions adjacent either side of the pass transistor structure, the first doped region defined by the predetermined distance; depositing a spacer dielectric layer; etching back the spacer dielectric layer to leave an unetched spacer dielectric layer portion overlying the first doped region while forming a sidewall spacer of a predetermined width overlying a first portion of the second doped region; and, carrying out a second ion implantation process to form a relatively higher dopant concentration in a second portion of the second doped region.

REFERENCES:
patent: 6395621 (2002-05-01), Mizushima et al.
patent: 6468855 (2002-10-01), Leung et al.
patent: 6642098 (2003-11-01), Leung et al.
patent: 6670664 (2003-12-01), Tzeng et al.
patent: 6784048 (2004-08-01), Leung et al.

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