Method for designing an integrated circuit defect monitor

Details Method for designing an integrated circuit defect monitor Method for designing an integrated circuit defect monitor

2006-08-15

2006-08-15

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C714S726000

Reexamination Certificate

active

07093213

ABSTRACT:
A method and system for designing a test structure. The method including: defining and placing test circuit pins in an integrated circuit design; routing one or more fat wires, each fat wire routed between a set of the test circuit pins; processing each fat wire into a continuous wire and one or more corresponding wire segments adjacent to the continuous wire, the continuous wire separated from the one or more corresponding wire segments by a space; and connecting the continuous wire and the one or more wire segments to circuit elements of a defect monitor scan chain, the circuit elements previously inserted into the integrated circuit design.

REFERENCES:
patent: 5703789 (1997-12-01), Beausang et al.
patent: 6708317 (2004-03-01), Grisenthwaite
patent: 6836877 (2004-12-01), Dupenloup

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