Double-gate structure fin-type transistor

Details Double-gate structure fin-type transistor Double-gate structure fin-type transistor

2006-02-14

2006-02-14

Kang, Donghee (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S330000, C257S331000, C257S332000, C438S212000, C438S259000, C438S270000, C438S271000

Reexamination Certificate

active

06998676

ABSTRACT:
A semiconductor device has a fin-type transistor formed in a projecting semiconductor region. The projecting semiconductor region is formed on a major surface of a semiconductor substrate of a first conductivity type. A gate electrode of the fin-type transistor is formed on at least opposed side surfaces of the projecting semiconductor region, with a gate insulating film interposed. Source and drain regions are formed in the projecting semiconductor region such that the source and drain regions sandwich the gate electrode. A channel region of the first conductivity type is formed in the projecting semiconductor region between the source and drain regions. The following relationship is established:in-line-formulae description="In-line Formulae" end="lead"?TFIN≧(∈/4qNCH)1/2in-line-formulae description="In-line Formulae" end="tail"?where TFINis a width of the projecting semiconductor region, NCHis an impurity concentration in the channel region, ∈ is a dielectric constant of a semiconductor material of the projecting semiconductor region, and q is an elementary charge.

REFERENCES:
patent: 2002/0036290 (2002-03-01), Inaba et all.
patent: 2-263473 (1990-10-01), None
patent: 3-245573 (1991-11-01), None
patent: 5-48109 (1993-02-01), None
patent: 8-139325 (1996-05-01), None
patent: 2002-118255 (2002-04-01), None
G. Pei et al., “FinFet Design Considerations Based on 3-D Simulation and Analytical Modeling,” IEEE Transactions on Electron Devices, vol. 49, No. 8, Aug. 2002, pp. 1411-1419.

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