Semiconductor memory device and precharge control method

Details Semiconductor memory device and precharge control method Semiconductor memory device and precharge control method

2006-02-28

2006-02-28

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S063000

Reexamination Certificate

active

07006396

ABSTRACT:
A semiconductor memory device that quickly precharges a bit line and shortens the cycle time for accessing the memory cells. The semiconductor memory device includes a memory cell array having a plurality of memory cells. A bit line is connected to the plurality of memory cells. A plurality of precharge circuits are connected to the bit line to precharge the bit line to a predetermined potential. A timing control circuit generates a timing signal. The precharge control circuit controls the precharge circuits in response to the timing signal such that the precharge circuits are activated sequentially from the one farthest from the timing control circuit to the one closest to the timing control circuit.

REFERENCES:
patent: 5717625 (1998-02-01), Hasegawa et al.
patent: 5894442 (1999-04-01), Okamura
patent: 6515913 (2003-02-01), Kajigaya et al.
patent: 08-063971 (1996-03-01), None
patent: 09-231758 (1997-09-01), None

Affiliated with

Also associated with

Rating

Semiconductor memory device and precharge control method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device and precharge control method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and precharge control method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3687475