Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-02-28
2006-02-28
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S234000
Reexamination Certificate
active
07005337
ABSTRACT:
The present invention provides a method for parallel production of an MOS transistor in an MOS area of a substrate and a bipolar transistor in a bipolar area of the substrate. The method includes generating an MOS preparation structure in the MOS area, wherein the MOS preparation structure includes an area provided for a channel, a gate dielectric, a gate electrode layer and a mask layer on the gate electrode layer. Further, a bipolar preparation structure is generated in the bipolar area, which includes a conductive layer and a mask layer on the conductive layer. For determining a gate electrode and a base terminal area, common structuring of the gate electrode layer and the conductive layer is performed. Further, the method includes simultaneous generation of isolating spacing layers on side walls of the gate electrode layer in the MOS area and the conductive layer in the bipolar area by depositing a first and second spacing layer. In the MOS area, the isolating spacing layers serve for defining areas to be doped and in the bipolar area for the isolation of a base area and an emitter area. Subsequently, selective etching of the first spacing layer and the second spacing layer is performed in the MOS area and the bipolar area.
REFERENCES:
patent: 5354699 (1994-10-01), Ikeda et al.
patent: 5622887 (1997-04-01), Miwa et al.
patent: 5641692 (1997-06-01), Miwa et al.
patent: 5824560 (1998-10-01), Van Der Wel et al.
patent: 5970332 (1999-10-01), Pruijmboom et al.
patent: 6001676 (1999-12-01), Sawada et al.
patent: 6103560 (2000-08-01), Suzuki
patent: 6440787 (2002-08-01), Yoshihisa
patent: 6815317 (2004-11-01), Schafbauer et al.
patent: 2004/0185611 (2004-09-01), Berthold et al.
patent: 0 746 032 (1996-12-01), None
patent: 0 851 486 (1998-01-01), None
patent: 63-244768 (1988-10-01), None
patent: 5-6961 (1993-01-01), None
patent: 200040758 (2000-02-01), None
patent: 2001203288 (2001-07-01), None
patent: WO 96/30940 (1996-10-01), None
patent: WO 96/30941 (1996-10-01), None
Berthold Adrian
Boeck Josef
Holz Juergen
Klein Wolfgang
Chaudhari Chandra
Infineon - Technologies AG
Maginot Moore & Beck
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