Method for forming polysilicon floating gate

Details Method for forming polysilicon floating gate Method for forming polysilicon floating gate

2006-12-12

2006-12-12

Weiss, Howard (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S468000

Reexamination Certificate

active

07148105

ABSTRACT:
A floating gate memory cell comprises a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer. The deposition environment is chosen so that the grain size of at least a portion of the floating gate opposite the first insulation layer is about 50–500 Å.

REFERENCES:
patent: 4748133 (1988-05-01), Griswold
patent: 4945393 (1990-07-01), Beltram et al.
patent: 4963506 (1990-10-01), Liaw et al.
patent: 5017308 (1991-05-01), Iijima et al.
patent: 5017980 (1991-05-01), Gill et al.
patent: 5147813 (1992-09-01), Woo
patent: 5445982 (1995-08-01), Hwang
patent: 5711998 (1998-01-01), Shufflebotham
patent: 5751637 (1998-05-01), Chen et al.
patent: 5753134 (1998-05-01), Biebl
patent: 5863706 (1999-01-01), Komatsu et al.
patent: 5874129 (1999-02-01), Beinglass et al.
patent: 5972765 (1999-10-01), Clark et al.
patent: 6013551 (2000-01-01), Chen et al.
patent: 6023093 (2000-02-01), Gregor et al.
patent: 6114722 (2000-09-01), Jan et al.
patent: 6143632 (2000-11-01), Ishida et al.
patent: 6218245 (2001-04-01), Xiang et al.
patent: 6221705 (2001-04-01), Rost et al.
patent: 6252270 (2001-06-01), Gregor et al.
patent: 6268068 (2001-07-01), Heuer et al.
patent: 6268086 (2001-07-01), Honbo et al.
patent: 6326274 (2001-12-01), Rost et al.
patent: 6373092 (2002-04-01), Okumoto
patent: 6509217 (2003-01-01), Reddy
patent: 6670241 (2003-12-01), Kamal et al.
patent: 6861339 (2005-03-01), Chen et al.
patent: 2004/0007733 (2004-01-01), Luoh
Mitani, Y., et al., “Highly Reliable Gate Oxide under Fowler-Nordheim Electron Injectionby Deuterium Pyrogentic Oxidation and Deuterated Poly-Si Deposition”, Dec. 10, 2000, IEDM Tech. Dig. Inter., p. 343-6.
Kwon, Hyungshin et al., “Electrical Characteristics of Ultrathin Gate Oxide Prepared by Postoxidation Anealing in ND3,” Appl. Phys. Let. 76:6, 772-773 (Feb. 7, 2000).
Dorsch, Jeff, “Applied Debuts RTP System,” Electronic News, Sep. 20, 1999, 3 pages.
“Characterizing Very Thin ONO Gates with Laser Spectroscopic Ellipsometry” Rudolph Technologies, Inc. Application Reports (2001) http://www.rudolphtech.com/reports/VeryThinONOGates.htm, 3 pages.
Lammers, David, “Chip makers bang away at metal gates,” EETIMES, Nov. 26, 2002, 3 pages.
Dipert, Brian, “Exotic Memories, Diverse Approaches,” EDN, Apr. 26, 2001, 56-70.
Wilson, Ron, “Flash gets a quantum makeover at IEDM,” EETIMES, Dec. 13, 2002, 4 pages.
“Polysilicon: The Successor Technology,” http://www.wtec.org/loyola/dsply—jp/c5—s5.htm (Jun. 1992), 3 pages.
Kahler, U. et al., “Size related Properties of silicon nanoparticles from decomposition of SiOx,” Max-Planck-Institut für Mikrostrukturphysik, 2000 Annual Report, 38-39. http://www.mpi-halle.mpg.de/annual—reports/2000.pdf/jb—results—14. pdf.
Minch, Bradley A., “The K-Input Floating-Gate MOS (FGMOS) Transistor” Sep. 20, 2002, http://people.ece.cornell.edu/minch/talks/FGMOSTdevicelayout.pdf, 22 pages.
“Flash Memory Technology,” Integrated Circuit Engineering Corporation (1997) 10-1 through 10-16. http://smithsonianchips.si.edu/ice/cd/MEMORY97/SEC10.PDF.
“The future is clear with Toshiba: Polysilicon”, accessed Nov. 3, 2004, http://www/toshiba-europe.com/computers/tnt/tft, 1 page.
Higher Resolution, The Future is clear with Toshiba, http://www.toshiba-europe.com/computers/tnt/tft/resolution.htm (2002), 1 page.
Polysilicon TFT, The Future is clear with Toshiba, http://www.toshiba-europe.com/computers/tnt/tft/ (2002), 1 page.
Polysilicon Explained, The future is clear with Toshiba, http://www.toshiba-europe.com/computers/tnt/tft/explained.htm (2002), 1 page.

Affiliated with

Also associated with

Rating

Method for forming polysilicon floating gate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming polysilicon floating gate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming polysilicon floating gate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3678173