FPGA configuration memory with built-in error correction...

Details FPGA configuration memory with built-in error correction... FPGA configuration memory with built-in error correction...

2006-11-28

2006-11-28

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S725000, C714S766000, C714S758000, C326S038000, C326S039000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07143329

ABSTRACT:
A system and method are disclosed for error correction in a programmable logic device (PLD). A frame circuit retrieves data from each column of configuration memory of the PLD, and a check memory stores of a plurality of check words. A buffer circuit is coupled to the check memory and to the frame circuit. The buffer circuit assembles blocks of data from data retrieved by the frame circuit and from corresponding check words in the check memory. A plurality of storage elements are provided for storage of status information. A check circuit is coupled to the storage elements and to the buffer circuit. Each block is checked by the check circuit using an error correcting code, and data indicating detected errors is stored in the storage elements.

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