Method of producing an integrated circuit configuration

Details Method of producing an integrated circuit configuration Method of producing an integrated circuit configuration

2006-02-14

2006-02-14

Pham, Hoai (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S672000, C438S643000, C438S653000

Reexamination Certificate

active

06998338

ABSTRACT:
In an integrated circuit configuration, above a first conductive structure which is embedded in a first insulating layer there are arranged a first barrier layer and a second insulating layer, in which a contact hole is provided which reaches down to the first conductive structure. Above the first barrier layer, the side walls of the contact hole are provided with spacers which act as a diffusion barrier and which reach down to the surface of the first barrier layer. A second conductive structure is arranged in the contact hole. The second conductive structure is conductively connected to the first conductive structure. During the production of the contact hole, the spacers prevent deposition of material from the first conductive structure on the surface of the second insulating layer.

REFERENCES:
patent: 5308793 (1994-05-01), Taguchi et al.
patent: 5612254 (1997-03-01), Mu et al.
patent: 5739579 (1998-04-01), Chiang et al.
patent: 5821168 (1998-10-01), Jain
patent: 5847460 (1998-12-01), Liou et al.
patent: 5966634 (1999-10-01), Inohara et al.
patent: 5969422 (1999-10-01), Ting et al.
patent: 6100184 (2000-08-01), Zhao et al.
patent: 6136682 (2000-10-01), Hegde et al.
patent: 6150272 (2000-11-01), Liu et al.
patent: 6197688 (2001-03-01), Simpson
patent: 6221780 (2001-04-01), Greco et al.
patent: 6251772 (2001-06-01), Brown
patent: 6335570 (2002-01-01), Mori et al.
patent: 6472304 (2002-10-01), Chittipeddi et al.
patent: 2002/0000665 (2002-01-01), Barr et al.
patent: 2002/0005582 (2002-01-01), Nogami et al.
patent: 2002/0019131 (2002-02-01), Ohtsuka et al.
patent: 2002/0098673 (2002-07-01), Yeh et al.
patent: 0 798 778 (1997-10-01), None
patent: 0 892 428 (1999-01-01), None
patent: 9 181 180 (1997-06-01), None
patent: 11 317 446 (1999-11-01), None
“A High Performance 3.97 μm2CMOS SRAM Technology Using Self-Aligned Local Interconnect and Copper Interconnect Metallization” (Woo et al.), 1998 Symposium on VLSI Technology Digest of Technical Papers, pp. 12-13.
“A High-Performance Sub-0.25 μm CMOS Technology with Multiple Thresholds and Copper Interconnects” (Su et al.), 1998 Symposium on VLSI Technology Digest of Technical Papers, pp. 18-19.

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