Method for prevention of latch-up of CMOS devices

Details Method for prevention of latch-up of CMOS devices Method for prevention of latch-up of CMOS devices

1997-01-28

2000-04-04

Quach, T. N.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438224, 438237, 438430, H01L 2130, H01L 21335

Patent

active

060460792

ABSTRACT:
A MOSFET integrated circuit device comprises a lightly doping a semiconductor substrate, with wells formed within the substrate doped with an opposite value dopant, forming a plurality of doped regions within the surface of the substrate and within the surface of the wells, the improvement comprising opening a trench about the periphery of the wells, and filling the trench with a relatively highly conductive material as a guard structure.

REFERENCES:
patent: 4671851 (1987-06-01), Beyer et al.
patent: 4805008 (1989-02-01), Yao et al.
patent: 4884117 (1989-11-01), Neppl et al.
patent: 4927777 (1990-05-01), Hsu et al.
patent: 4939567 (1990-07-01), Kenney
patent: 4960726 (1990-10-01), Lechaton et al.
patent: 5071777 (1991-12-01), Gahle
patent: 5096843 (1992-03-01), Kodaira
patent: 5106777 (1992-04-01), Rodder
patent: 5137837 (1992-08-01), Chang et al.
patent: 5158900 (1992-10-01), Lau et al.
patent: 5200639 (1993-04-01), Ishizuka
patent: 5348906 (1994-09-01), Harajiri
Wolf, et al., Silicon Processing, vol. 1, Lattice Press, 1986, pp. 283-291, 303-314.

Affiliated with

Also associated with

Rating

Method for prevention of latch-up of CMOS devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for prevention of latch-up of CMOS devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for prevention of latch-up of CMOS devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-364485