Word line enable timing determination circuit of a memory...

Details Word line enable timing determination circuit of a memory... Word line enable timing determination circuit of a memory...

2006-06-27

2006-06-27

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100

Reexamination Certificate

active

07068559

ABSTRACT:
A word line enable timing determination circuit of a memory device and method of determining word line enable timing in a memory device may be configured to adjust enable timing at which to activate a word line for at least one read/write command input to the memory device. This may be based on whether the memory device is performing a hidden refresh operation. In an example, and when a read/write command is input to the memory device, a word line for the read/write command may be activated after a first delay if the memory device is not executing a hidden refresh operation. Otherwise, a word line for the read/write command is activated after a second delay.

REFERENCES:
patent: 5617551 (1997-04-01), Corder
patent: 6275437 (2001-08-01), Kim et al.
patent: 6928020 (2005-08-01), Takahashi et al.

Affiliated with

Also associated with

Rating

Word line enable timing determination circuit of a memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Word line enable timing determination circuit of a memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Word line enable timing determination circuit of a memory... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3631245