Methods and systems for estimating reticle bias states

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07089528

ABSTRACT:
Disclosed are methods and systems for estimating a reticle bias state for a process system, that include computing a difference between control data provided to the process system and error data based on a process system output(s), and estimating the reticle bias state based on weighted measures associated with the control data, the weighted measures being based on the number of data points included in the difference. The methods and systems include associating the reticle bias state estimate with a first quality factor, computing at least one weighted measure based on a number of data elements associated with the reticle, using the weighted measure(s) to provide a computed reticle bias state estimate and an associated computed quality factor, and, comparing the computed quality factor with the first quality factor to determine whether to update the reticle bias state estimate with the computed reticle bias state estimate.

REFERENCES:
patent: 6429930 (2002-08-01), Littau et al.
patent: 6453457 (2002-09-01), Pierrat et al.
patent: 6513151 (2003-01-01), Erhardt et al.
patent: 6526164 (2003-02-01), Mansfield et al.
patent: 2003/0138706 (2003-07-01), Progler et al.
patent: 2005/0216877 (2005-09-01), Pack et al.

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