Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2006-05-09
2006-05-09
Elamin, A. (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S401000, C713S500000, C713S501000, C713S502000, C713S503000
Reexamination Certificate
active
07043652
ABSTRACT:
In a memory system having a memory controller20and at least one DRAM30, the memory controller20receives a continuous and alternate inversion signal as a pseudo clock signal from the DRAM30, and generates an internal reception clock signal for a DQ signal on the basis of the continuous and alternate inversion signal and a base clock signal. Then, the memory controller20counts the number of the receiving internal clocks from the moment an OUT1 command is issued to the DRAM30until a high-level data signal is received as the DQ data signal from the DRAM30, and retains the count result as the number of delay clocks. Thus, the memory controller20can receive read data (DQ signal) on the basis of the internal reception clock signal when time equivalent to the number of the delay clocks passes after the read command is issued.
REFERENCES:
patent: 5892719 (1999-04-01), Kanagawa
patent: 5995430 (1999-11-01), Yabe
patent: 6081477 (2000-06-01), Li
patent: 6154418 (2000-11-01), Li
patent: 6442102 (2002-08-01), Borkenhagen et al.
patent: 6691214 (2004-02-01), Li et al.
patent: 6704881 (2004-03-01), Li et al.
patent: 6760856 (2004-07-01), Borkenhagen et al.
patent: 6845460 (2005-01-01), Lee et al.
patent: 6877079 (2005-04-01), Yoo et al.
patent: 6889336 (2005-05-01), Schoenfeld et al.
patent: 11-007335 (1999-01-01), None
patent: 11-039869 (1999-02-01), None
patent: 11-167515 (1999-06-01), None
patent: 2000-148656 (2000-05-01), None
patent: 2002-082830 (2002-03-01), None
patent: 2002-531966 (2002-09-01), None
patent: WO 00/33200 (2000-06-01), None
Japanese Office Action dated Sep. 22, 2004.
SLDRAM Inc. SLD4M18DR400 4 MEG X 18 SLDRAM Datasheet. 1998, p. 1-14.
Elamin A.
Elpida Memory Inc.
Katten Muchin & Rosenman LLP
LandOfFree
Calibration method and memory system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Calibration method and memory system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Calibration method and memory system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3623085