Method of forming fin field effect transistor

Details Method of forming fin field effect transistor Method of forming fin field effect transistor

2006-06-06

2006-06-06

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S592000

Reexamination Certificate

active

07056781

ABSTRACT:
According to some embodiments, a fin type active region is formed under an exposure state of sidewalls on a semiconductor substrate. A gate insulation layer is formed on an upper part of the active region and on the sidewalls, and a device isolation film surrounds the active region to an upper height of the active region. The sidewalls are partially exposed by an opening part formed on the device isolation film. The opening part is filled with a conductive layer that partially covers the upper part of the active region, forming a gate electrode. Source and drain regions are on a portion of the active region where the gate electrode is not. The gate electrode may be easily separated and problems causable by etch by-product can be substantially reduced, and a leakage current of channel region and an electric field concentration onto an edge portion can be prevented.

REFERENCES:
patent: 6417047 (2002-07-01), Isobe
patent: 6548859 (2003-04-01), Maegawa
patent: 6642090 (2003-11-01), Fried et al.
patent: 6846734 (2005-01-01), Amos et al.
patent: 6855588 (2005-02-01), Liao et al.
patent: 2003/0122186 (2003-07-01), Sekigawa et al.
Park et al., “A 40nm Body-Tied FinFET (OMEGA MOSFET) using Bulk Si Wafer” Physica E, vol. 19, Issues 1-2, pp. 6-12 (Jul. 2003).

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