Data output controller for memory device

Details Data output controller for memory device Data output controller for memory device

2006-06-06

2006-06-06

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S233100, C365S185090

Reexamination Certificate

active

07057943

ABSTRACT:
Disclosed is a data output controller for a memory device. The data output controller for a memory device, the data output controller comprising a control part for generating a first pulse control signal and a second pulse control signal through a combination of an internal clock signal outputted from a DLL means and a pulse signal enabled during a time in which a number of clocks of the internal clock signal, corresponding to a burst length of the memory device, is counted, a data output buffer unit controlled by the first plus control signal, and a data strobe signal buffer unit controlled by the second pulse control signal.

REFERENCES:
patent: 5535171 (1996-07-01), Kim et al.
patent: 5903514 (1999-05-01), Sawada
patent: 6212126 (2001-04-01), Sakamoto
patent: 6249483 (2001-06-01), Kim
patent: 6317369 (2001-11-01), Kubo et al.

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