Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-03-28
2006-03-28
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07020817
ABSTRACT:
The delay characteristic of a chip under test on which a function test is performed first is detected by performing an edge search for stabilizing the test without awaiting the delay characteristic to be stabilized and the result of detection is stored in a memory. By using the delay characteristic stored in the memory, the function test is performed repeatedly on the chip under test till NG (FAIL) occurs. When NG occurs, the function test is performed repeatedly till the NG count of the chip under test reaches a first specified number. If the NG count exceeds the first specified number, the foregoing process is repeated starting from the edge search. If the NG count reaches a second specified number, the chip under test is determined to be defective and the test is ended.
REFERENCES:
patent: 6237115 (2001-05-01), Ting et al.
patent: 6598192 (2003-07-01), McLaurin et al.
patent: 6658604 (2003-12-01), Corbin et al.
patent: 6693436 (2004-02-01), Nelson
patent: 11-111796 (1999-04-01), None
De'cady Albert
Kerveros James C.
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
LandOfFree
Method for testing semiconductor chips and semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for testing semiconductor chips and semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for testing semiconductor chips and semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3604439