Method to provide a triple well in an epitaxially based CMOS...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S228000, C438S202000

Reexamination Certificate

active

07008836

ABSTRACT:
A method to provide a triple well in an epitaxially based CMOS or B:CMOS process comprises the step of implanting the triple well prior to the epitaxial deposition.

REFERENCES:
patent: 5470766 (1995-11-01), Lien
patent: 5776807 (1998-07-01), Ronkainen et al.
patent: 5780899 (1998-07-01), Hu et al.
patent: 5880014 (1999-03-01), Park et al.
patent: 5895251 (1999-04-01), Kim
patent: 6242793 (2001-06-01), Colombo et al.
patent: 6255153 (2001-07-01), Ryoo
patent: 6258641 (2001-07-01), Wong et al.
patent: 6300209 (2001-10-01), Oh
patent: 6366499 (2002-04-01), Wang et al.
patent: 6525394 (2003-02-01), Kuhn et al.
patent: 2003/0020106 (2003-01-01), Tran

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