Boundary scan register for differential chip core

Details Boundary scan register for differential chip core Boundary scan register for differential chip core

2006-01-24

2006-01-24

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06990618

ABSTRACT:
An integrated circuit including a first cell configured to perform boundary scan testing, and an I/O node coupled to the first cell, wherein the I/O node is configured to carry a first differential signal. A level translator may be coupled between the I/O node and the first cell, wherein the level translator is configured to translate the first differential signal into a single ended signal. A level translator may be coupled between the I/O node and the first cell, wherein the level translator is configured to translate a single ended signal into the first differential signal. Core logic may be coupled to the first cell, wherein the core logic is configured to process a second differential signal, and a level translator may be coupled between the core logic and the first cell, wherein the level translator is configured to translate the second differential signal into a single ended signal.

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