Analyzing instruction completion delays in a processor

Details Analyzing instruction completion delays in a processor Analyzing instruction completion delays in a processor

2006-05-16

2006-05-16

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

Reexamination Certificate

active

07047398

ABSTRACT:
A method and system for identifying instruction completion delays for a group of instructions in a computer processor. Each instruction in the group of instructions has a status indicator that identifies what is preventing that instruction from completing execution. Examples of completion delays are cache misses, data dependencies or simply the time required for an execution unit in the computer processor to process the instruction. As each instruction finishes executing, its associated status indicator is cleared to indicate that the instruction is no longer waiting to execute. The last instruction to execute is the instruction that is holding up completion of the entire group, and thus the cause for the completion delay of the last instruction is recorded as the cause of completion delay for the entire group.

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Intel, “Pentium® Pro Family Developer's Manual, vol. 3: Operating System Writer's Guide,” Dec. 1995, p. B1-B6.

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