Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-05-02
2006-05-02
Vu, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S314000
Reexamination Certificate
active
07037782
ABSTRACT:
A multiple-bit cell transistor includes a P type silicon substrate, a gate insulation layer, a pair of N type source/drain regions, a pair of tunnel insulation layers, and a pair of floating gates. The silicon substrate is formed with a projection while the floating gates each are positioned on one of opposite side walls of the projection. Inter-polycrystalline insulation layers each are formed on one of the floating gates. A control gate faces the top of the projection via the gate insulation layer. An N type region is formed on each side of the projection and contacts the source/drain region adjoining it. The cell transistor lowers a required write voltage, broadens a current window, and enhances resistance to inter-band tunneling.
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Paper No. 29-p-YC-4, The Joint Meeting of Engineers of Applied Physics of Japan, p. 38.
Birch & Stewart Kolasch & Birch, LLP
Innotech Corporation
Vu David
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