Silicon-on-nothing fabrication process

Details Silicon-on-nothing fabrication process Silicon-on-nothing fabrication process

2006-07-18

2006-07-18

Kebede, Brook (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21414

Reexamination Certificate

active

07078298

ABSTRACT:
A method to fabricate a silicon-on-nothing device on a silicon substrate is provided. The disclosed silicon-on-nothing device is fabricated on an isolated floating silicon active area, thus completely isolated from the silicon substrate by an air gap. The isolated floating silicon active area is fabricated on a silicon germanium layer with a surrounding isolation trench. A plurality of anchors is then fabricated to anchor the silicon active area to the silicon substrate before selectively etching the silicon germanium layer to form the air gap. Isolation trench fill and planarization complete the formation of the isolated floating silicon active area. The silicon-on-nothing device on the isolated floating silicon active area can be polysilicon gate or metal gate and with or without raised source and drain regions.

REFERENCES:
patent: 6274421 (2001-08-01), Hsu et al.
patent: 6352899 (2002-03-01), Sakiyama et al.
patent: 6368960 (2002-04-01), Hsu et al.
patent: 6472266 (2002-10-01), Yu et al.
patent: 6486025 (2002-11-01), Liu et al.
patent: 6501120 (2002-12-01), Tu et al.
patent: 6713356 (2004-03-01), Skotnicki et al.
patent: 6727186 (2004-04-01), Skotnicki et al.
patent: 2799307 (2001-04-01), None
patent: WO 57480 (2000-09-01), None
patent: WO 0057480 (2000-09-01), None
Robert Chau, Jack Kavalieros, Brian Doyle, Anand Murthy, Nancy Paulsen, Daniel Lionberger, Douglas Barlage, Reza Arghavani, Brian Roberds, Mark Doczy, “a 50nm depleted-substrate CMOS transistor (DST)”, IEDM, p. 621, 2001.
Risho Koh, “Buried layer engineering to reduce the Drain-Induced Barrier Lowering of sub-0.05 μm SOI-MOSFET”, Japanese Journal of Applied Physics, vol. 38 (1999) pp. 2294-2299, Part 1, No. 4B, Apr. 1999.
Malgorzata Jurczak, Thomas Skotnicki, M. Paoli, B. Tormen, J. Martins, Jorge Luis Regolini, Didier Dutartre, Pascal Ribot, D. Lenoble, Roland Pantel, Stephanie Monfray, “Silicon-On-Nothing (SON)—an innovative process for advanced CMOS”, IEEE Transactions on Electron Devices, vol. 47, No. 11, Nov. 2000, pp. 2179-2187.
S. Monfray, T. Skotnicki, Y. Morand, S. Descombes, M. Paoli, P. Ribot, A. Talbot, D. Dutartre, F. Leverd, Y. Lefriec, R. Pantel, M. Haond, D. Renaud, M-E. Nier, C. Vizioz, D. Louis, N. Buffett, “First 80nm SON (Silicon-On-Nothing) MOSFETs with perfect morphology and high electrical performance”, IEDM, 2001.
Tsutomu Sato, Hideaki Nii, Masayuki Hatano, Keiichi Takenaka, Hisataka Hayashi, Kazutaka Ishigo, Tomoyuki Hirano, Kayuhiko Ida, Nobutoshi Aoki, Tatsuya Ohguro, Kazumi Ino, Ichiro Mizushima, Yoshitaka Tsunashima, “SON (Silicon-On-Nothing) MOSFET using ESS (Empty Space in Silicon) technique for SoC applications”, IEDM Tech. Digest, p. 809, 2001.
Ichiro Mizushima, Tsutomu Sato, Yoshitaka Tsunashima, “SON (Silicon-On-Nothing) MOSFET using ESS (Empty Space in Silicon) technique”, Electrochemical Society International Semiconductor Technology Conference 2002, Sep. 12, 2002, Tokyo, Japan.

Affiliated with

Also associated with

Rating

Silicon-on-nothing fabrication process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Silicon-on-nothing fabrication process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon-on-nothing fabrication process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3574581