Method for identification of sub-optimally placed circuits

Details Method for identification of sub-optimally placed circuits Method for identification of sub-optimally placed circuits

2006-01-24

2006-01-24

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06990648

ABSTRACT:
A method for identifying, in a VLSI chip design, circuits placed in an region of wiring congestion which can be replaced such that wiring tracks are freed up due to decreased net lengths without any pin to pin segment increasing in length. Circuits placed within the region of wiring congestion are identified and examined to determine the circuits they connect to. The placements of the connected circuits are analyzed to derive a rectangle of connectivity. Each of the originally identified circuits are then checked to determine if they are placed within their associated rectangle of connectivity. If not, the distance between the circuit and rectangle is calculated along with a recommended placement location, both of which are reported along with the circuit. The recommended placement location is a point along the border of the rectangle such that replacement of the circuit at the location reduces all circuit net lengths without increasing any pin to pin segment. In this way, wiring tracks are freed up without any potential for increased path delays.

REFERENCES:
patent: 5587923 (1996-12-01), Wang
patent: 5673201 (1997-09-01), Malm et al.
patent: 5784289 (1998-07-01), Wang
patent: 5859781 (1999-01-01), D'Haeseleer et al.
patent: 5875117 (1999-02-01), Jones et al.
patent: 5903461 (1999-05-01), Rostoker et al.
patent: 5930499 (1999-07-01), Chen et al.
patent: 5984510 (1999-11-01), Guruswamy et al.
patent: 6123736 (2000-09-01), Pavisic et al.
patent: 6292929 (2001-09-01), Scepanovic et al.
patent: 6301693 (2001-10-01), Naylor et al.
patent: 6353918 (2002-03-01), Carothers et al.
patent: 6415427 (2002-07-01), Nitta et al.
patent: 6493658 (2002-12-01), Koford et al.
patent: 6557145 (2003-04-01), Boyle et al.
patent: 6609243 (2003-08-01), Evans et al.
patent: 6637016 (2003-10-01), Gasanov et al.
patent: 6671859 (2003-12-01), Naylor et al.
patent: 6766500 (2004-07-01), Donelly et al.
patent: 6832362 (2004-12-01), Nuber
patent: 6904585 (2005-06-01), Brittain et al.
patent: 6912704 (2005-06-01), Teig
patent: 2001/0018759 (2001-08-01), Andreev et al.
patent: 2003/0018947 (2003-01-01), Tieg et al.
patent: 2003/0229878 (2003-12-01), Nuber
patent: 2004/0040007 (2004-02-01), Harn
patent: 2004/0078770 (2004-04-01), Miller et al.
patent: 03074873 (1991-03-01), None
Frezza et al., “SPAR: a schematic place and route system”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, No. 7, Jul. 1993, pp. 956-973.
Kastner et al., “Pattern routing: use and theory for increasing predictability and avoiding coupling”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, No. 7, Jul. 2002, pp. 777-790.
Sham et al., “Routability-driven floorplanner with buffer block planning”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, No. 4, Apr. 2, 2003, pp. 470-480.
Wang et al., “Modeling and minimization of routing congestion”, Proceedings of the ASP-DAC 2000 Asia and South Pacific Design Automation Conference, Jan. 25, 2000, pp. 185-190.
Krishna et al., “Technique for planning of terminal locations of leaf cells in cell-based design with routing considerations”, 1998 Proceedings of Eleventh International Conference on VLSI Design, Jan. 4, 1998, pp. 53-58.
Wang et al., “Congestion minimization during placement”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, No. 10, Oct. 2000, pp. 1140-1148.

Affiliated with

Also associated with

Rating

Method for identification of sub-optimally placed circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for identification of sub-optimally placed circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for identification of sub-optimally placed circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3546854