Timing adjustment of clock signals in a digital circuit

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C706S013000

Reexamination Certificate

active

06993672

ABSTRACT:
A digital system that performs a specified function by performing digital processing according to one or more clock signals is provided with a plurality of delay elements which are respectively inserted in a plurality of clock circuits that supply the clock signals in the digital system and each of which is composed of a circuit element that changes a delay time according to a value indicated by a control signal, and a plurality of holding circuits that hold a plurality of control signals to be given to the plurality of delay elements. In the plurality of holding circuits, a value of the control signals held by these holding circuits is changed by external devices according to a probabilistic search technique so that the digital system operates correctly in relation to operation timing.

REFERENCES:
patent: 4286330 (1981-08-01), Isaacson
patent: 4697242 (1987-09-01), Holland et al.
patent: 4796259 (1989-01-01), Troy
patent: 5077677 (1991-12-01), Murphy et al.
patent: 5224056 (1993-06-01), Chene et al.
patent: 5475830 (1995-12-01), Chen et al.
patent: 5506959 (1996-04-01), Cockburn
patent: 5719515 (1998-02-01), Danger
patent: 6269451 (2001-07-01), Mullarkey
patent: 6327552 (2001-12-01), Nemani et al.
patent: 6480832 (2002-11-01), Nakisa
patent: 6578176 (2003-06-01), Wang et al.
patent: A-3-117210 (1991-05-01), None
patent: A-4-23172 (1992-01-01), None
patent: A-6-3419 (1994-01-01), None
patent: A-6-75018 (1994-03-01), None
patent: A-6-295319 (1994-10-01), None
patent: A-7-134700 (1995-05-01), None
patent: A-9-325949 (1997-12-01), None
patent: A-9-330350 (1997-12-01), None
patent: A-10-21279 (1998-01-01), None
patent: A-10-111861 (1998-04-01), None
AIST Press Release, “AIST Team Develops Genetic Algorithm-Based Method to Adjust Clock Timing that Allows Power Consumption to be Halved in High-Speed LSIs: Adjusted Clock Timing Provides Enhanced Clock Frequencies and Reduced Design Times”, Jun. 11, 2003 (in Japanese w/English Summary).
U.S. Appl. No. 09/397,636, filed Sep. 1999, Tetsuya Higuchi et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Timing adjustment of clock signals in a digital circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Timing adjustment of clock signals in a digital circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing adjustment of clock signals in a digital circuit will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3533034

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.