Semiconductor memory device for dynamically storing data...

Static information storage and retrieval – Systems using particular element – Semiconductive

Reexamination Certificate

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C365S164000, C257S314000

Reexamination Certificate

active

07075820

ABSTRACT:
A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.

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Takashi Ohsawa, et al., “Memory Design Using a One-Transistor Gain Cell on SOI”, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1510-1522.
Kazumi Inoh, et al., “FBC (Floating Body Cell) for Embedded Dram on SOI”, 2003 Symposium on VLSI Technology Digest of Technical Papers, 2003, pp. 63-64.

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