ESD protection devices and methods to reduce trigger voltage

Details ESD protection devices and methods to reduce trigger voltage ESD protection devices and methods to reduce trigger voltage

2005-02-22

2005-02-22

Zarabian, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S173000, C257S174000, C257S355000, C257S356000, C257S357000, C257S358000, C257S359000, C257S361000, C257S362000, C257S363000

Reexamination Certificate

active

06858900

ABSTRACT:
ESD protection devices and methods of forming them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process and breakdown-enhanced layers, ESD protection devices with a lower trigger voltage are provided. The NMOS structure for ESD protection according to the present invention has islands, a control gate and breakdown-enhanced layers. These islands as well as the breakdown-enhanced layers overlapping the drain region of the NMOS reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

REFERENCES:
patent: 5248892 (1993-09-01), Van Roozendaal et al.
patent: 5559352 (1996-09-01), Hsue et al.
patent: 5679971 (1997-10-01), Tamba et al.
patent: 5701024 (1997-12-01), Watt
patent: 5721439 (1998-02-01), Lin
patent: 6008080 (1999-12-01), Chuang et al.
patent: 6030871 (2000-02-01), Eitan
patent: 6034415 (2000-03-01), Johnson et al.
patent: 6046087 (2000-04-01), Lin et al.
patent: 6100141 (2000-08-01), Hsu
patent: 6114226 (2000-09-01), Chang et al.
patent: 6171891 (2001-01-01), Lee et al.
patent: 6229182 (2001-05-01), Van Lieverloo
patent: 6268256 (2001-07-01), Kuo
patent: 6444511 (2002-09-01), Wu et al.
patent: 6514839 (2003-02-01), Ker et al.
patent: 6703663 (2004-03-01), Lee et al.
patent: 20010010954 (2001-08-01), Lin et al.
patent: 20020070408 (2002-06-01), Schnaitter
patent: 20020076876 (2002-06-01), Ker et al.
patent: 20030141551 (2003-07-01), Hokazono et al.

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