Multiple buffer memory interface

Details Multiple buffer memory interface Multiple buffer memory interface

2005-06-14

2005-06-14

Auduong, Gene N. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S230080, C365S185090

Reexamination Certificate

active

06906964

ABSTRACT:
Disclosed herein are systems and apparatuses having memories with a multiple buffer memory interface. In one embodiment, an integrated memory device comprises: a memory array integrated on a substrate, and a multiple buffer memory interface integrated on the same substrate. The memory interface comprises multiple read buffers each associated with a different region of the memory array and configured to buffer only data for read operations on the associated region.

REFERENCES:
patent: 5963488 (1999-10-01), Inoue
patent: 6430103 (2002-08-01), Nakayama et al.
patent: 6760255 (2004-07-01), Conley et al.
“Double Data Rate (DDR) SDRAM”; 512Mb: x8, DDR 400 SDRAM Addendum, Micron Technology, Inc., 2003 (pp 1-8).
Andrew M. Spencer; “Nonvolatile Buffered Memory Interface,” U.S. patent application number not yet assigned, filed Jun. 27, 2003 (22 p.).
Richard L. Hilton et al.; “Assisted Memory System,” U.S. Appl. No. 10/384,053, filed Mar. 6, 2003 (21 p.).

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