Clock phase adjustment method, integrated circuit, and...

Details Clock phase adjustment method, integrated circuit, and... Clock phase adjustment method, integrated circuit, and...

2005-02-08

2005-02-08

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S233100

Reexamination Certificate

active

06853589

ABSTRACT:
The time required for access to a SDRAM (110) is extracted from the layout of an integrated circuit (1000), a first phase difference between an external clock SDCLKO and an internal clock ICLK is calculated, and the value of delay of the external clock signal or the internal clock signal in the integrated circuit (1000) is changed on the basis of the calculated first phase difference, whereby clock phase adjustment for the integrated circuit (1000) in the designing stage is realized.

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