Power consumption reducing circuit having word-line resetting ab

Details Power consumption reducing circuit having word-line resetting ab Power consumption reducing circuit having word-line resetting ab

1995-09-14

1997-02-11

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

36523003, 36523006, 3652385, G11C 700

Patent

active

056027842

ABSTRACT:
In a semiconductor memory device having word-line-resetting ability regulating transistors each placed between the corresponding one of a large number of word lines and the ground, each of the above word-line-resetting-ability regulating transistors is composed of first and second transistors connected in series. During standby, the gate voltage of the above second transistor is controlled to be at a set low value (e.g., a value of about 1 V, which is higher than the threshold voltage of the above resetting-ability regulating transistors by 0.2 to 0.5 V). During the operation of the semiconductor memory device, the gate voltage of the second transistor is controlled to be at a value (e.g., 3.3 V) lower than a value of a power source for row decoders (e.g., 5 V) and higher than the above set low value when the corresponding word line is selected, while it is controlled to be at the above set low value (1 V) when the corresponding word line is not selected. Consequently, a current resulting from a short circuit between a bit line and a word line and flowing from the bit line to the ground through the short-circuited portion and the word line can be suppressed during standby and an operating current flowing during operation can be suppressed, thereby reducing power consumption.

REFERENCES:
patent: 5265052 (1993-11-01), D'Arrigo et al.
patent: 5335205 (1994-08-01), Ogihara
patent: 5455789 (1995-10-01), Nakamura et al.

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