Low latency FIFO circuits for mixed asynchronous and...

Details Low latency FIFO circuits for mixed asynchronous and... Low latency FIFO circuits for mixed asynchronous and...

2005-02-01

2005-02-01

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S096000, C365S119000, C365S120000, C710S053000, C710S056000, C710S057000, C711S105000, C711S167000, C327S141000, C327S144000

Reexamination Certificate

active

06850092

ABSTRACT:
A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface configured to operate in accordance with the sender time domain and get interface configured to operate in accordance with the receiver time domain. The FIFO circuit includes an array of cells having a register and state controller indicative of the state of the cell. Each cell also has a put component part configured to operate according to the sender time domain including a put token passing circuit and put controller circuit. Each cell has get component part configured to operate according to the receiver time domain including a get token passing circuit and a get controller circuit. A mixed-clock relay station design interfaces a sender subsystem and a receiver subsystem working at different time domains, and where the latency between sender and receiver is large.

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