4. Electronic digital logic circuitry
  5. Clocking or synchronizing of logic stages or gates

Tiberiu Chelcea

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Low latency FIFO circuit for mixed clock systems

Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate

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Low latency FIFO circuits for mixed asynchronous and...

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate

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Profile ID: LFUS-PAI-P-2872329

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