Memory having a latching BICMOS sense amplifier

Details Memory having a latching BICMOS sense amplifier Memory having a latching BICMOS sense amplifier

1992-10-05

1994-08-30

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

3652256, 36523008, 307530, G11C 700

Patent

active

053434285

ABSTRACT:
A memory (80) having a latching BICMOS sense amplifier (20) includes a reduced power data retention mode. The latching BICMOS sense amplifier (20) senses and amplifies differential data signals corresponding to data from a selected memory cell (85). A latch (35) temporarily retains the logic state of the differential data signals in response to a clock signal. The reduced power data retention mode is provided by utilizing selectable current sources (66-75) responsive to an output enable signal. The latching BICMOS sense amplifier (20) allows for very high speed operation, yet provides for reduced power consumption while in a latched state.

REFERENCES:
patent: 4551641 (1985-11-01), Pelley, III
patent: 4817051 (1989-03-01), Chang
patent: 5034636 (1991-07-01), Reis et al.
patent: 5103117 (1992-04-01), Voorman et al.
patent: 5103121 (1992-04-01), Wendell et al.
patent: 5151879 (1992-09-01), Hsueh et al.
patent: 5206550 (1993-04-01), Mehta
patent: 5239506 (1993-08-01), Dachtera et al.

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