Layouts for CMOS SRAM cells and devices

Details Layouts for CMOS SRAM cells and devices Layouts for CMOS SRAM cells and devices

2005-03-22

2005-03-22

Le, Dung A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S380000, C257S381000

Reexamination Certificate

active

06870231

ABSTRACT:
SRAM cells and devices are provided. The SRAM cells may share connections with neighboring cells, including ground, power supply voltage and/or bit line connections. SRAM cells and devices are also provided that include first and second active regions disposed at a semiconductor substrate. Parallel first and second gate electrodes cross over the first and second active regions. One end of the first active region adjacent to the first gate electrode is electrically connected to the second active region adjacent to the first gate electrode through a first node line parallel to the first gate electrode, and the other end of the first active region adjacent to the second gate electrode is electrically connected to the second active region adjacent to the second gate electrode through a second node line parallel to the second gate electrode. The first node line is electrically connected to the second gate electrode through a first local interconnection crossing over the first node line, and the second node line is electrically connected to the first gate electrode through a second local interconnection crossing over the second node line. Additionally, a word line may be in direct contact with gate electrodes of transfer transistors of the SRAM cells.

REFERENCES:
patent: 5654572 (1997-08-01), Kawase
patent: 6642555 (2003-11-01), Ishida
patent: 20010030372 (2001-10-01), Mori et al.
patent: 20010042926 (2001-11-01), Kumagai et al.
patent: 20020001899 (2002-01-01), Ito
patent: 10006643 (2000-02-01), None
Official Letter (English Translation) for corresponding German Application No. 103 00 038 0 33, May 11, 2004.

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