Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2005-04-19
2005-04-19
Le, Don (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C331S181000
Reexamination Certificate
active
06882182
ABSTRACT:
A tunable clock distribution system is used to minimize the power dissipation of a clock distribution network in an integrated circuit. The tunable clock distribution system provides a tunable inductance on the clock distribution network to adjust a resonant frequency in the tunable clock distribution system. The inductance is tuned so that the resonant frequency of the tunable clock distribution system approaches the frequency of the clock signal on the clock distribution network. As the resonant frequency of the tunable clock distribution system approaches the frequency of the clock signal, the power dissipation of the clock distribution network decreases. Some embodiments also provide a tunable capacitance on the clock distribution network to adjust the resonant frequency of the tunable clock distribution system.
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Conn Robert O.
Kingsley Christopher H.
Lawman Gary R.
Lesea Austin H.
Kanzaki Kim
Le Don
Mao Edward S.
Xilinx , Inc.
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