Semiconductor fabrication process using transistor spacers...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S275000

Reexamination Certificate

active

06864135

ABSTRACT:
A semiconductor fabrication process is disclosed wherein a first gate (108, 114) is formed over a first portion of a semiconductor substrate (102) and a second gate (114, 108) is formed over a second portion of the substrate (102). A spacer film (118) is deposited over substrate (102) and first and second gates (108, 114). First spacers (126) are then formed on sidewalls of the second gate (114) and second spacers (136) are formed on sidewalls of first gate (108). The first and second spacers (126, 136) have different widths. The process may further include forming first source/drain regions (128) in the substrate laterally disposed on either side of the first spacers (126) and second source/drain regions (138) are formed on either side of second spacers (136). The different spacer widths may be achieved using masked first and second spacer etch processes (125, 135) having different degrees of isotropy. The spacer etch mask and the source/drain implant mask may be common such that p-channel transistors have a different spacer width than n-channel transistors.

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patent: 20020098633 (2002-07-01), Budge et al.
patent: 2257563 (1993-01-01), None

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