Flash/dynamic random access memory field programmable gate...

Details Flash/dynamic random access memory field programmable gate... Flash/dynamic random access memory field programmable gate...

2005-05-10

2005-05-10

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S063000, C365S189110

Reexamination Certificate

active

06891769

ABSTRACT:
A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.

REFERENCES:
patent: 4408304 (1983-10-01), Nishizawa et al.
patent: 6016268 (2000-01-01), Worley
patent: 6137714 (2000-10-01), Voogel

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