Semiconductor device including impurity layer having...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S248000, C438S424000, C438S433000

Reexamination Certificate

active

06841440

ABSTRACT:
A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N+-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.

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patent: 6261920 (2001-07-01), Oyamatsu
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patent: 6287920 (2001-09-01), Chatterjee et al.
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patent: 6541825 (2003-04-01), Kuroi et al.
patent: 61-99376 (1986-05-01), None
patent: 10-189951 (1998-07-01), None
Wolf and Tauber; “Silicon Processing for the VLSI Era vol. 1: Process Technology”; p. 298; copyright 1986, Lattice Press; Sunset Beach, CA.

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