Inter-block interface circuit and system LSI

Details Inter-block interface circuit and system LSI Inter-block interface circuit and system LSI

2005-04-19

2005-04-19

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S080000, C326S026000

Reexamination Certificate

active

06882175

ABSTRACT:
An inter-block interface circuit which effectively prevents occurrences of inconveniences (for example, such that a shoot-through current flows due to unsteady potential in wiring) caused by switching off a power supply of a block, using simple circuitry, in LSI such that signals are communicated between the blocks and the power supplies of the blocks are interrupted independently. In the circuit, gate circuits112and114are respectively provided in blocks102and104that communicate signals with one another, and interface control circuit202dynamically controls respective input levels of gate circuits112and114. In other words, the circuit202fixes an input level of gate circuit112or114in a block whose power supply is ON to “L”, and thereby compulsively fixes an output level of the gate circuit to “L”.

REFERENCES:
patent: 5583457 (1996-12-01), Horiguchi et al.
patent: 6208171 (2001-03-01), Kumagai et al.
patent: 6256252 (2001-07-01), Arimoto
patent: 6275096 (2001-08-01), Hsu et al.
patent: 1320889 (2001-11-01), None
patent: 56112123 (1981-09-01), None
patent: 61081660 (1986-04-01), None
patent: 61134821 (1986-06-01), None
patent: 02003272 (1990-01-01), None
patent: 05165551 (1993-07-01), None
patent: 10084274 (1998-03-01), None
patent: 2000207884 (2000-07-01), None
patent: 2000299436 (2000-10-01), None
patent: 2001-093275 (2001-04-01), None
patent: WO 9851012 (1998-11-01), None
English Language Abstract of JP Appln. No. 2001-093275, Apr. 2001.
English Language Abstract of JP Appln. No. 2000-299436, Oct. 2000.
English Language Abstract of JP Appln. No. 2000-207884, Jul. 2000.
English Language Abstract of JP Appln. No. 10-084274, Mar. 1998.
English Language Abstract of JP Appln. No. 05-165551, Feb. 1993.
English Language Abstract of JP Appln. No. 02-003272, Jan. 1990.
English Language Abstract of JP Appln. No. 61-134821, Jun. 1986.
English Language Abstract of JP Appln. No. 61-081660, Apr. 1986.
English Language Abstract of JP Appln. No. 56-112123, Sep. 1981.

Affiliated with

Also associated with

Rating

Inter-block interface circuit and system LSI does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Inter-block interface circuit and system LSI, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Inter-block interface circuit and system LSI will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3418477