Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-09-06
2005-09-06
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S264000, C438S267000, C438S266000, C438S592000, C438S593000, C257S413000, C257S414000, C257S415000
Reexamination Certificate
active
06939764
ABSTRACT:
Concurrently forming self-aligned silicides on word lines and contacts of a memory device facilitates reduced resistance and/or reduced device sizing. The word-line silicide is formed at a stage significantly later than in standard processing, decreasing concerns of thermal stability of the silicide, thus allowing the use of lower-resistance silicides. In addition, by forming contacts to drain and/or source regions prior to forming the silicide for the word lines, aspect ratios for the contact holes or trenches are reduced for a given pitch, thus improving effectiveness of processing to remove material from these holes and trenches or allowing the use of a smaller pitch. By providing a process for the application of a silicide in array source interconnects, a single array source interconnect can couple an entire row of memory cells, thereby reducing the number of contacts made to an array ground.
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Chen Chun
Wolstenholme Graham
Le Dung A.
Leffert Jay & Polglaze PA
Micro)n Technology, Inc.
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