Methods for fabricating and operating electrically erasable and

Details Methods for fabricating and operating electrically erasable and Methods for fabricating and operating electrically erasable and

1995-05-31

1997-04-22

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

H01L 218247

Patent

active

056228791

ABSTRACT:
The invention relates to a novel electrically programmable and erasable memory cell.
The cell comprises a single transistor, which is a floating gate transistor and has no selection transistor. Means are provided for establishing a high capacitive coupling between the drain (12) and the floating gate (18). The capacitive coupling between the source (10) and the floating gate is low, as is normally the case. Preferably, the control gate (22) only partly covers the floating gate (18). Another part of the floating gate is covered by a semiconductor layer (26) connected to the drain. It is the latter layer which establishes the high capacitive coupling according to the invention. Programming can then take place by the Fowler-Nordheim effect with the source under high impedance, i.e. without hot electron effect.

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T. Nozaki et al., "A 1 Mbit EEPROM with MONOS Memory Cell for Semiconductor Disk Application" Proceedings of the Symposium on VLSI Circuits Honolulu IEEE, Sep. 7, 1990, pp. 101-102.

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