System and method for operating a memory array

Details System and method for operating a memory array System and method for operating a memory array

2005-03-01

2005-03-01

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S230020, C365S063000

Reexamination Certificate

active

06862224

ABSTRACT:
A method and apparatus for storing and retrieving data in a second, or higher, order prefetch architecture memory integrated circuit. The method includes storing multiple bits of data in memory cells at various electrical distances from an output buffer and retrieving those memory bits concurrently for output. By outputting the bits in a fixed burst order, according to which a bit from a memory cell closer to the output buffer is output before a bit from a memory cell farther from the output buffer, the output time of the data bit from the closer memory cell can be used to mask a portion of the transit time of the bit from the farther memory cell. The apparatus includes memory cells at various locations for storing data bits, an address decoder adapted to store and retrieve multiple bits in a fixed burst order, and a multiplexer.

REFERENCES:
patent: 5625603 (1997-04-01), McClure et al.
patent: 6031785 (2000-02-01), Park et al.
patent: 6335889 (2002-01-01), Onodera
patent: 6721233 (2004-04-01), Wilford et al.

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