Integrated circuit with timing adjustment mechanism and method

Details Integrated circuit with timing adjustment mechanism and method Integrated circuit with timing adjustment mechanism and method

2005-09-27

2005-09-27

Cottingham, John R. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S375000, C713S401000, C713S500000, C713S503000, C713S600000, C327S002000, C327S009000, C327S141000, C327S233000, C375S147000, C375S149000, C375S219000, C375S316000, C375S240280

Reexamination Certificate

active

06950956

ABSTRACT:
An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.

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