Method of forming offset spacer manufacturing for critical...

Details Method of forming offset spacer manufacturing for critical... Method of forming offset spacer manufacturing for critical...

2005-05-31

2005-05-31

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S595000, C438S710000, C438S756000

Reexamination Certificate

active

06900104

ABSTRACT:
A method for forming an offset spacer adjacent a CMOS gate structure with improved critical dimension control including providing a substrate that has a gate structure; forming at least one oxide layer over the substrate; forming at least one nitride layer over the at least one oxide layer; dry etching the at least one nitride layer in a first dry etching process to expose a first portion of the at least one oxide layer; carrying out a wet etching process to remove the first portion of the at least one oxide layer; and, dry etching the at least one nitride layer in a second dry etching process to remove the at least one nitride layer leaving a second portion of the at least one oxide layer to form an oxide offset spacer along sidewalls of the gate structure.

REFERENCES:
patent: 2003/0235966 (2003-12-01), Kim et al.
patent: 2004/0248369 (2004-12-01), Wang et al.

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